Integrated circuitry

ABSTRACT

A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired local interconnect. Conductive material is formed therewithin. A second isolation material is deposited over the first isolation material, over the conductive material within the isolation trench and within the line trench. At least some first and second isolation material is removed in at least one common removing step. Integrated circuitry includes a substrate comprising trench isolation material. A local interconnect line is received within a trench formed within the isolation material. The local interconnect includes at least two different conductive materials. One of the conductive materials lines the trench. Another of the conductive materials is received within a conductive trench formed by the one. Other implementations are disclosed.

TECHNICAL FIELD

[0001] This invention relates to methods of forming conductive lines,and to integrated circuitry.

BACKGROUND OF THE INVENTION

[0002] The reduction in memory cell and other circuit size implementedin high density dynamic random access memories (DRAMs), static randomaccess memories (SRAMs), logic and other circuitry is a continuing goalin semiconductor fabrication. Implementing electric circuits involvesconnecting isolated devices through specific electric paths. Whenfabricating silicon and other semiconductive materials into integratedcircuits, conductor devices built into semiconductive substrates need tobe isolated from one another. Such isolation typically occurs in theform of LOCOS grown field oxide, and more recently in isolation trenchand refill field isolation regions.

[0003] Conductive lines, for example transistor gate lines, are formedover substrates. Some lines run globally over large areas of thesubstrate. Others are much shorter and associated with very smallportions of the integrated circuitry. This invention was principallymotivated in making processing and structural improvements involvinglocal interconnects.

SUMMARY

[0004] The invention includes methods of forming conductive lines, andintegrated circuitry. In but one implementation, a method of forming alocal interconnect includes forming an isolation trench within asemiconductor substrate. A first trench isolation material is depositedover the semiconductor substrate and to within the isolation trench.First trench isolation material is removed effective to form a linetrench within the isolation material into a desired local interconnectconfiguration. Conductive material is formed within the line trench. Asecond trench isolation material is deposited over the first trenchisolation material, over the conductive material within the isolationtrench and within the line trench. At least some first and second trenchisolation material is removed from the substrate in at least one commonremoving step.

[0005] In one implementation, a method of forming a local interconnectincludes providing a bulk semiconductor substrate having a firstconductivity type background region, an adjacent second conductivitytype background region and a boundary extending therebetween. Anisolation trench is formed within the bulk semiconductor substrate overand along the boundary. A trench isolation material is deposited overthe bulk semiconductor substrate and to within the isolation trench.Trench isolation is removed effective to form a line trench within theisolation material into a desired local interconnect configuration.Conductive material is formed to within the line trench.

[0006] In one implementation, integrated circuitry includes asemiconductor substrate comprising trench isolation material. A localinterconnect line is received within a trench formed within the trenchisolation material. The local interconnect line includes at least twodifferent conductive materials. One of the conductive materials linesthe trench. Another of the conductive materials is received within aconductive trench formed by the one.

[0007] Other implementations and aspects are contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a schematic of exemplary integrated circuitry.

[0010]FIG. 2 is a diagrammatic sectional view of a semiconductor waferfragment in process in accordance with an aspect of the invention.

[0011]FIG. 3 is a view of the FIG. 2 wafer fragment at a processing stepsubsequent to that shown by FIG. 2.

[0012]FIG. 4 is a view of the FIG. 3 wafer fragment at a processing stepsubsequent to that shown by FIG. 3.

[0013]FIG. 5 is a view of the FIG. 4 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0014]FIG. 6 is a top plan view of a larger portion of the waferfragment in process, the above fragmentary views being taken throughline X-X in FIG. 6.

[0015]FIG. 7 is a view of the FIG. 5 wafer fragment at a processing stepsubsequent to that shown by FIG. 5.

[0016]FIG. 8 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 7.

[0017]FIG. 9 is a view of the FIG. 8 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

[0018]FIG. 10 is a view of the FIG. 9 wafer fragment at a processingstep subsequent to that shown by FIG. 9.

[0019]FIG. 11 is a top plan view like FIG. 6, but shown at a processingstep subsequent to that of FIGS. 6 and 10.

[0020]FIG. 12 is a view of a portion of the FIG. 11 wafer fragment astaken through line 12-12 in FIG. 11.

[0021]FIG. 13 is a view of the FIG. 12 wafer fragment at a processingstep subsequent to that shown by FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0023] The invention contemplates methods of forming localinterconnects, and any integrated circuitry involving a localinterconnect line, in accordance with the literal wording of the claims.The invention is described with respect to but one exemplary integratedcircuit shown in FIG. 1. Such depicts a cross-coupled inverter circuitry10 comprising n-type transistors T1n and T2n, and p-type transistors T3pand T4p. A local interconnect L1 interconnects the gates of T2n and T4pwith source/drain regions of T1n and T3p.

[0024] Referring to FIG. 2, a semiconductor wafer fragment is indicatedgenerally with reference 12. Such comprises a bulk semiconductorsubstrate having a first conductivity-type background region 16 adjacenta second conductivity-type background region 18, and a boundary 20extending therebetween. An exemplary preferred material for bulksubstrate 14 is monocrystalline, for example monocrystalline silicon,with region 16 being shown lightly background doped with “n” typeimpurity and region 18 being lightly background doped with “p” typeimpurity. In the context of this document, the term “semiconductorsubstrate” or “semiconductive substrate” is defined to mean anyconstruction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above. Also in the context of this document, the terms “layer”and “material” encompass both the singular and the plural unlessotherwise indicated. A pad oxide layer 22 is formed over bulk substrate14. An exemplary thickness is 100 Angstroms. A masking layer 24 isformed over layer 22. An exemplary material is silicon nitride depositedto an exemplary thickness of 900 Angstroms.

[0025] Referring to FIG. 3, an isolation trench 26 is formed within bulksemiconductor substrate material 14, which is laterally centered andextends along p-type/n-type boundary 20. Such will be utilized to forminterwell isolation, with an exemplary open width of depicted trench 26being about 0.5 micron. An exemplary depth within substrate material 14is 3000 Angstroms. Such provides but one example of forming an isolationtrench within a semiconductor substrate. Further in the depicted andpreferred embodiment, the isolation trench is formed in bulk substratematerial, although the invention is in no way so limited. For purposesof the continuing discussion, isolation trench 26 can be considered ashaving opposing longitudinal sidewalls 25 in the depicted cross-section.Further in the depicted embodiment, isolation trench 26 is formed to belaterally centered over boundary 20.

[0026] Referring to FIG. 4, a first trench isolation material 28 isdeposited over substrate 14 and within isolation trench 26. A preferredmethod of forming layer 28 is by high density plasma chemical vapordeposition. Sidewalls 25 of trench 26 are preferably thermally oxidized(not shown) before or after deposition of material 28.

[0027] Referring to FIGS. 5 and 6, exemplary active areas 34 can beseen. First trench isolation material 28 is removed effective to form aline trench 30 within the isolation material into a desired localinterconnect configuration. Such removing preferably comprisesphotolithography and chemical etching, and forms at least a portion ofline trench 30 to be laterally centered within isolation trench 26between sidewalls 25, and laterally centered over boundary 20. In thepreferred embodiment, FIG. 6 depicts that line trench 30 includesextensions 32 which do not extend to an edge of the trench isolationmaterial proximate active area substrate material/regions 34.Accordingly at this point in the process in the preferred embodiment,local interconnect trench 30 does not extend to connect with theillustrated active areas. FIG. 6 also depicts exemplary transistor gateoutlines 36, which would typically not be formed at this point in thepreferred embodiment process. Regardless, it can be seen that the farright illustrated edge of local interconnect trench 30 is also spacedfrom, and therefore does not connect with, the right illustratedtransistor gate outline 36, in this preferred embodiment.

[0028] Conductive material is formed within trench 30 to form at least aportion of the local interconnect being formed. FIG. 7 illustrates butone exemplary embodiment wherein a first conductive material 40 isformed, preferably by depositing, to within trench 30 to form aconductive lining therewithin. In one preferred embodiment, layer 40 isformed of an oxidation resistant material. Exemplary materials includetungsten silicide and nitrogen-rich titanium nitride. In such preferredembodiment, such thereby forms an oxidation resistant lining within linetrench 30. In an alternate considered embodiment, the oxidationresistant liner material might be insulative as opposed to conductive.An exemplary insulative oxidation resistant liner material is siliconnitride. A second conductive material 42, different from firstconductive material 40, is deposited to within line trench 30 on (incontact with) conductive lining 40. Exemplary materials for layer 42include tungsten and doped polysilicon. Of course, a singe conductivematerial could be utilized or more than two conductive materialsutilized.

[0029] Referring to FIG. 8, conductive materials 40/42 are recessedwithin line trench 30 after their deposition. An exemplary preferredprocess for doing so would be one or more suitable timed chemicaletching(s). Such provides but a few preferred examples of formingconductive materials to within line trench 30.

[0030] Referring to FIG. 9, a second trench isolation material 46 isdeposited over first trench isolation material 28, over recessedconductive material 40/42 within isolation trench 26, and within linetrench 30. Second trench isolation material 46 might be the samecomposition as first trench isolation material 28, or be of differentcomposition. More preferably, such are the same material, with highdensity plasma deposited oxide being the preferred example. In theillustrated and preferred embodiment, second trench isolation material46 is formed on (in contact with) conductive materials 40/42.

[0031] Referring to FIG. 10, at least some first trench isolationmaterial 28 and at least some second trench isolation material 46 areremoved from the substrate in at least one common removing step. Apreferred process includes chemical mechanical polishing (CMP). In thedepicted preferred embodiment, such polishing is shown conductedeffective to substantially stop on nitride masking layer 24. Of course,polishing could also be continued to remove more material, for examplepolishing through nitride layer 24 and pad oxide layer 22. Further byway of example only, nitride layer 24 and pad oxide layer 22 might beselectively chemically etched in processing subsequent to that depictedby FIG. 10.

[0032] Referring to FIGS. 11 and 12, an insulative material 50 is formedover trench isolation material 28/46 and over conductive material 40/42.Exemplary materials for layer 50 include undoped and doped oxides, forexample borophosphosilicate glass, phosphosilicate glass, and otherdoped and undoped silicon dioxides. Further at this point in theprocess, gate lines 36 have been fabricated prior to deposition of layer50, and layers 24 and 22 have been removed. Contact openings 52 areetched into insulative material 50 to bridge over and between activearea substrate material 34 and conductive material 40/42 within linetrench 30.

[0033] Referring to FIG. 13, a conductor is formed within contactopenings 52 which electrically connects the conductive material with theactive area substrate material, and with the far right illustrated gate52 as shown in FIG. 6. Such thereby effectively extends the conductivelocal interconnect line to electrically connect with the depictedsource/drain regions and transistor gate line.

[0034] The invention also contemplates integrated circuitry comprising alocal interconnect line independent of any method of fabrication.

[0035] The invention may have particular application in the formation oflocal interconnects in the periphery of SRAM circuitry. Processing andcircuitry in accordance with the invention can serve to provide an extralevel of interconnect, thereby freeing up space for higher levelinterconnects at upper levels of the fabrication. By embedding an extralevel of interconnect in trench isolation areas, tighter metallizationand interconnect density might be achievable.

[0036] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a local interconnect, comprising: providing abulk semiconductor substrate having a first conductivity type backgroundregion, an adjacent second conductivity type background region and aboundary extending therebetween; forming an isolation trench within thebulk semiconductor substrate laterally centered over and along theboundary; depositing a first trench isolation material over the bulksemiconductor substrate and to within the isolation trench; chemicallyetching the first trench isolation material effective to form a linetrench within the isolation material at least a portion of which islaterally centered within the isolation trench and laterally centeredover the boundary; depositing conductive material within the line trenchand recessing it within the line trench after depositing it; depositinga second trench isolation material the same as the first trenchisolation material over the first trench isolation material, over therecessed conductive material within the isolation trench and within theline trench; and removing at least some first and second trenchisolation material from the substrate in at least one common removingstep.
 2. The method of claim 1 wherein the at least one common removingstep comprises CMP.
 3. The method of claim 1 wherein the formingconductive material within the line trench comprises depositing at leasttwo different composition conductive materials to within the linetrench.
 4. The method of claim 1 wherein the line trench in the trenchisolation material does not extend to an edge of the trench isolationmaterial proximate active area substrate material, and furthercomprising after the removing: forming insulative material over thefirst and second trench isolation materials and over the conductivematerial; etching a contact opening into the insulative material whichbridges over and between said active area substrate material and saidconductive material; and forming a conductor within the contact openingwhich electrically connects said conductive material with said activearea substrate material.
 5. A method of forming a local interconnect,comprising: forming an isolation trench within a semiconductorsubstrate; depositing a first trench isolation material over thesemiconductor substrate and to within the isolation trench; removingfirst trench isolation material effective to form a line trench withinthe isolation material into a desired local interconnect configuration;forming conductive material within the line trench; depositing a secondtrench isolation material over the first trench isolation material, overthe conductive material within the isolation trench and within the linetrench; and removing at least some first and second trench isolationmaterial from the substrate in at least one common removing step.
 6. Themethod of claim 5 wherein the substrate comprises a bulk monocrystallinesubstrate, and the isolation trench is formed in bulk monocrystallinesubstrate material.
 7. The method of claim 5 wherein the first andsecond trench isolation materials are the same in composition.
 8. Themethod of claim 5 wherein the first and second trench isolationmaterials are different in composition.
 9. The method of claim 5 whereinthe removing of the first trench isolation material to form the linetrench comprises chemical etching.
 10. The method of claim 5 wherein theat least one common removing step comprises CMP.
 11. The method of claim5 wherein the forming conductive material within the line trenchcomprises depositing conductive material and recessing it within theline trench after the depositing.
 12. The method of claim 5 wherein theforming conductive material within the line trench comprises depositingat least two different composition conductive materials to within theline trench.
 13. A method of forming a local interconnect, comprising:forming an isolation trench within a semiconductor substrate; depositinga trench isolation material over the semiconductor substrate and towithin the isolation trench; removing trench isolation materialeffective to form a line trench within the isolation material into adesired local interconnect configuration; forming first conductivematerial to within the trench to form a conductive lining within theline trench; and depositing a second conductive material different fromthe first conductive material to within the line trench on theconductive lining.
 14. The method of claim 13 wherein the removing formsat least a portion of the line trench to be laterally centered betweensidewalls of the isolation trench in at least one cross section.
 15. Themethod of claim 13 comprising covering the second conductive materialwith insulative material the same as the trench isolation material. 16.The method of claim 15 wherein at least some of the insulative materialis received within the line trench and on the conductive material.
 17. Amethod of forming a local interconnect, comprising: forming an isolationtrench within a semiconductor substrate; depositing a trench isolationmaterial over the semiconductor substrate and to within the isolationtrench; removing trench isolation material effective to form a linetrench within the isolation material into a desired local interconnectconfiguration; forming an oxidation resistant liner material to withinthe trench to form an oxidation resistant lining within the line trench;and depositing conductive material to within the line trench on theoxidation resistant lining.
 18. The method of claim 17 wherein theoxidation resistant liner material is insulative.
 19. The method ofclaim 17 wherein the oxidation resistant liner material is conductive.20. The method of claim 17 wherein the removing forms at least a portionof the line trench to be laterally centered between sidewalls of theisolation trench in at least one cross section.
 21. The method of claim17 comprising covering the conductive material with insulative materialthe same as the trench isolation material.
 22. The method of claim 21wherein at least some of the insulative material is received within theline trench and on the conductive material.
 23. A method of forming alocal interconnect, comprising: forming an isolation trench within asemiconductor substrate, the isolation trench having opposinglongitudinal sidewalls in at least one cross section; depositing atrench isolation material over the semiconductor substrate and to withinthe isolation trench; removing trench isolation material effective toform a line trench within the isolation material into a desired localinterconnect configuration which is laterally centered between theopposing isolation trench sidewalls in the one cross section; andforming conductive material to within the line trench.
 24. The method ofclaim 23 wherein the forming conductive material within the line trenchcomprises depositing conductive material and recessing it within theline trench after the depositing.
 25. The method of claim 23 wherein theforming conductive material within the line trench comprises depositingat least two different composition conductive materials to within theline trench.
 26. The method of claim 23 wherein the substrate comprisesa bulk monocrystalline substrate, and the isolation trench is formed inbulk monocrystalline substrate material.
 27. A method of forming a localinterconnect, comprising: providing a bulk semiconductor substratehaving a first conductivity type background region, an adjacent secondconductivity type background region and a boundary extendingtherebetween; forming an isolation trench within the bulk semiconductorsubstrate over and along the boundary; depositing a trench isolationmaterial over the bulk semiconductor substrate and to within theisolation trench; removing trench isolation material effective to form aline trench within the isolation material into a desired localinterconnect configuration; and forming conductive material to withinthe line trench.
 28. The method of claim 27 comprising forming theisolation trench to be laterally centered over the boundary.
 29. Themethod of claim 27 comprising forming the line trench to be laterallycentered over the boundary.
 30. The method of claim 27 comprisingforming the isolation trench and the line trench to be laterallycentered over the boundary.
 31. The method of claim 27 comprisingforming the line trench to be laterally centered between longitudinalsidewalls of the isolation trench in at least one cross section.
 32. Amethod of forming a local interconnect comprising: etching a line trenchinto a desired line configuration into trench isolation material formedrelative to a semiconductor substrate, the line trench in the trenchisolation material not extending to an edge of the trench isolationmaterial proximate active area substrate material; and formingconductive material over the substrate which at least partially fillsthe trench.
 33. The method of claim 32 wherein the substrate comprises abulk monocrystalline substrate, and the isolation trench is formed inbulk monocrystalline substrate material.
 34. The method of claim 32wherein the forming conductive material within the line trench comprisesdepositing conductive material and recessing it within the line trenchafter the depositing.
 35. The method of claim 32 wherein the formingconductive material within the line trench comprises depositing at leasttwo different composition conductive materials to within the linetrench.
 36. A method of forming a local interconnect comprising: etchinga line trench into a desired line configuration within trench isolationmaterial formed relative to a semiconductor substrate, the line trenchin the trench isolation material not extending to an edge of the trenchisolation material proximate active area substrate material; formingconductive material over the substrate which at least partially fillsthe trench; forming insulative material over the trench isolationmaterial and over the conductive material; etching a contact openinginto the insulative material which bridges over and between said activearea substrate material and said conductive material; and forming aconductor within the contact opening which electrically connects saidconductive material with said active area substrate material.
 37. Themethod of claim 36 wherein the forming conductive material within theline trench comprises depositing conductive material and recessing itwithin the line trench after the depositing.
 38. The method of claim 36wherein the forming conductive material within the line trench comprisesdepositing at least two different composition conductive materials towithin the line trench.
 39. The method of claim 36 wherein the substratecomprises a bulk monocrystalline substrate, and the isolation trench isformed in bulk monocrystalline substrate material.
 40. Integratedcircuitry comprising: a semiconductor substrate comprising trenchisolation material; and a local interconnect line received within atrench formed within the trench isolation material, the localinterconnect line comprising at least two different conductivematerials, one of the conductive materials lining the trench, another ofthe conductive materials being received within a conductive trenchformed by the one.
 41. The integrated circuitry of claim 40 wherein thetrench isolation material has laterally opposing sidewalls along atleast one region, the local interconnect line being laterally centeredbetween the sidewalls in the one region.
 42. The integrated circuitry ofclaim 40 wherein the semiconductor substrate comprises bulkmonocrystalline material, the trench isolation material being receivedwithin the bulk monocrystalline material.
 43. Integrated circuitrycomprising: a semiconductor substrate comprising trench isolationmaterial, the trench isolation material comprising opposing sidewalls inat least one cross section; and a local interconnect line receivedwithin a trench formed within the trench isolation material, the localinterconnect line being laterally centered between the isolationmaterial sidewalls in the one cross section.
 44. The integratedcircuitry of claim 43 wherein the semiconductor substrate comprises bulkmonocrystalline material, the trench isolation material being receivedwithin the bulk monocrystalline material.
 45. Integrated circuitrycomprising: a bulk semiconductor substrate having a first conductivitytype background region, an adjacent second conductivity type backgroundregion and a boundary extending therebetween; trench isolation materialreceived within bulk semiconductor material of the substrate over theboundary; and a local interconnect line received within a trench formedwithin the trench isolation material and received along the boundary.46. The integrated circuitry of claim 45 wherein the trench isolationmaterial has laterally opposing sidewalls along at least one region, thelocal interconnect line being laterally centered between the sidewallsin the one region.
 47. The integrated circuitry of claim 45 wherein thelocal interconnect line is laterally centered over the boundary.
 48. Theintegrated circuitry of claim 45 wherein the trench isolation materialhas laterally opposing sidewalls along at least one region, the localinterconnect line being laterally centered between the sidewalls in theone region, the local interconnect line being laterally centered overthe boundary.